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Si 5 0 1 8 - EVB
EVALUATION BOARD FOR Si5018 SiPHYTM OC-48/STM-16 C L O C K A N D D A TA R E C O V E R Y IC W I T H F E C
Description
The Si5018 evaluation board provides a platform for testing and characterizing Silicon Laboratories Si5018 OC-48, STM-16, and 2.7 Gbps FEC clock and data recovery (CDR) device. All high-speed I/Os are ac coupled to ease interfacing to industry standard test equipment.
Features
Single 2.5 V power supply Differential I/Os ac coupled Simple jumper configuration
Function Block Diagram
Jitter Analyzer Pulse G enerator Z C = 50 Z C = 50 + REFCLK - + CLKO UT - Si5018 Pattern G enerator Z C = 50 Z C = 50 + DATAIN - + DATAO UT - Z C = 50 Z C = 50 Pattern Analyzer Z C = 50 Z C = 50 Scope
LOL PW RDN/CAL REXT 10 k Jum per SI5018-EVB Rev C Test Point
Rev. 1.0 12/02
Copyright (c) 2002 by Silicon Laboratories
SI5018-EVB-10
SI5018-EVB
Functional Description
The evaluation board simplifies characterization of the Si5018 OC-48, STM-16, and 2.7 Gbps FEC clock and data recovery (CDR) device by providing access to all of the Si5018 I/Os. Device performance can be evaluated by following the Test Configuration section below. Specific performance metrics include jitter tolerance, jitter generation, and jitter transfer. Power Supply The evaluation board requires one 2.5 V supply. Supply filtering is placed on the board to filter typical system noise components, however, initial performance testing should use a linear supply capable of supplying 2.5 V 5% dc. CAUTION: The evaluation board is designed so that the body of the SMA jacks and GND are shorted. Care must be taken when powering the PCB at potentials other than GND at 0.0 V and VDD at 2.5 V relative to chassis GND. Self-Calibration The Si5018 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal DSPLLTM. Self-calibration is initiated by a high-to-low transition of the PWRDN/CAL signal while a valid reference clock is supplied to the REFCLK input. On the SI5018-EVB board, a voltage detector IC is utilized to initiate self-calibration. The voltage detector drives the PWRDN/CAL signal low after the supply voltage has reached a specific voltage level. This circuit is described in Silicon Laboratories application note AN42. On the SI5018-EVB, the PWRDN/CAL signal is also accessible via a jumper located in the lower lefthand corner of the evaluation board. PWRDN/CAL is wired to the signal post adjacent to the 2.5 V post. Device Powerdown The CDR can be powered down via the PWRDN/CAL signal. When asserted the evaluation board will draw minimal current. PWRDN/CAL is controlled via one jumper located in the lower left-hand corner of the evaluation board. PWRDN/CAL is wired to the signal post adjacent to the 2.5 V post. CLKOUT, DATAOUT, DATAIN These high-speed I/Os are wired to the board perimeter on 30 mil (0.030 inch) 50 microstrip lines to the endlaunch SMA jacks as labeled on the PCB. These I/Os are ac coupled to simplify direct connection to a wide array of standard test hardware. Because each of these signals are differential both the positive (+) and negative (-) terminals must be terminated to 50 . Terminating only one side will adversely degrade the performance of the CDR. The inputs are terminated on the die with 50 resistors.
2
To improve the DATAOUT eye-diagram, short 100 transmission line segments precede the 50 highspeed traces. These segments increase the interface bandwidth from the chip to the 50 traces and reduce data inter-symbol-interference. Please refer to Silicon Laboratories application note AN43 for more details.
Note: The 50 termination is for each terminal/side of a differential signal, thus the differential termination is actually 50 + 50 = 100 .
REFCLK REFCLK is used to center the frequency of the DSPLLTM so that the device can lock to the data. Ideally the REFCLK frequency should be 1/128th, 1/32nd, or 1/16th the VCO frequency and must have a frequency accuracy of 100 PPM. Internally, the CDR automatically recognizes the REFCLK frequency within one of these three frequency ranges. Typical REFCLK frequencies are given in Table 1. REFCLK is ac coupled to the SMA jacks located on the top side of the evaluation board.
Table 1. Typical REFCLK Frequencies
SONET/SDH
19.44 MHz 77.76 MHz 155.52 MHz
Gigabit Ethernet
19.53 MHz 78.125 MHz 156.25 MHz
SONET/ SDH with 15/14 FEC
20.83 MHz 83.31 MHz 166.63 MHz
Ratio of VCO to REFCLK
128 32 16
Loss-of-Lock (LOL) LOL is an indicator of the relative frequency between the data and the REFCLK. LOL will assert when the frequency difference is greater than 600 PPM. In order to prevent LOL from de-asserting prematurely, there is hysterisis in returning from the out-of-lock condition. LOL will be de-asserted when the frequency difference is less than 300 PPM. LOL is wired to a test point which is located on the upper right-hand side of the evaluation board.
Test Configuration
The three critical tests that are typically performed on a CDR device are jitter transfer, jitter tolerance, and jitter generation. By connecting the Si5018 Evaluation Board as shown in Figure 1, all three measurements can be easily made. REFCLK should be within 100 PPM of the frequency selected from Table 1. PWRDN/CAL must be unjumpered.
Rev. 1.0
SI5018-EVB
Jitter Tolerance: Referring to Figure 1, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, a pattern analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test the Jitter Analyzer causes a modulation on the data pattern which drives the DATAIN ports of the CDR. The Bit-Error-Rate (BER) is monitored on the Pattern Analyzer. The modulation (jitter) frequency and amplitude is recorded when the BER approaches a specified threshold. Jitter Generation: Referring to Figure 1, this test requires a pattern generator, a clock source (synthesizer signal source), a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test there is no modulation of the Data Clock, so the data that is sent to the CDR is jitter free. The Jitter Analyzer measures the RMS and peak-to-peak jitter on the CDR CLKOUT. Thus, any jitter measured is jitter generated by the CDR. Jitter Transfer: Referring to Figure 1, this test requires a pattern generator, a clock source (synthesizer signal source), a modulation source, a jitter analyzer, and a pulse generator (all unconnected high-speed outputs must be terminated to 50 ). During this test the Jitter Analyzer modulates the data pattern and data clock reference. The modulated data clock reference is compared with the CLKOUT of the CDR. Jitter on CLKOUT relative to the jitter on the data clock reference is plotted versus modulation frequency at predefined jitter amplitudes.
Pulse Generator
2.5 V
Scope
DATAOUT-
Pattern Analyzer
GPIB
+- REFCLK+ REFCLK- + REFCLK - DATAOUT + -
DATAOUT+
DATAIN+ DATAIN-
+ DATAIN -
CLKOUT
+ -
CLKOUT+ CLKOUT-
SI5018-EVB
Pattern Generator
GPIB Clock
Data Clock+
Jitter Analyzer
GPIB
Synthesizer Signal Source
FM
Modulation Source
GPIB
Figure 1. Test Configuration for Jitter Tolerance, Transfer, and Generation
Rev. 1.0
3
U4 VCC 3
GND
1
2 7 11 14
VDDA VDDB VDDC VDDD
SIG 2 BODY J2 SIG 2 BODY JC 142-0701-801 1 0603 0.1uF JC 142-0701-801 C7 0603 0.1uF
GNDA GNDB GNDC GNDD GNDE
3 8 18 19 20
4
JP1 JP4 VDD VDD C13 0603 100pF C15 0603 100pF tantalum 10uF C16 0603 100pF C12 VDD C9 0805 Do Not Install
2.5V
L1
J9
1206 BLM31A601S
POS1
1
POS2
2
SI5018-EVB
MKDSN 2,5/3-5,08
V?
R2 2 0603 2.5k VDD OUT MAX6376XR23-T
U5 C4 1 LOL 6 0603 0.1uF C3 1 12 DOUT13
J3 BODY SIG J4 JC 142-0701-801 BODY SIG 0603 0.1uF JC 142-0701-801 2 2
J7 SIG 2 BODY J8 SIG 2 BODY 0603 0.1uF 10 JC 142-0701-801 9 DIN+ DIN1 JC 142-0701-801 C6 15 PWRDN/CAL 0603 0.1uF 1
C5
Rev. 1.0
4 5 REFCLK+ REFCLKJ1 1 C8 1 REXT R1 0603 10k
DOUT+
CLKOUTCLKOUT+
16 17 J5 C2 1 Si5018 0603 0.1uF C1 1 0603 0.1uF BODY SIG J6 JC 142-0701-801 BODY SIG JC 142-0701-801 2 2
Figure 2. Si5018 Schematic
SI5018-EVB
Bill of Materials
Si5018EVB Assy Rev B-02 BOM Reference Part Desc Part Number Manufacturer
C1,C2,C3,C4,C5, C6,C7,C8 CAP, SM, 0.1uF, 0603 C0603X7R160-104KNE C12 CAP, SM, 10 uF, TANTALUM, 3216 TA010TCM106KAR C13,C15,C16 CAP, SM, 100 pF, 16V, 0603 C0603C0G500101KNE JP1 J1,J2,J3,J4,J5,J6, J7,J8 J9 L1 R1 R2 U4 U5 PCB No Load C9 CONNECTOR, HEADER, 2X1 CONNECTOR, SMA, SIDE MOUNT CONNECTOR, POWER, 2 POS RESISTOR, SM, 0 OHM, 1206 RESISTOR, SM, 10K, 1%, 0603 RESISTOR, SM, 2.55K, 1%, 0603 MAX6376XR23-T Si5018 PRINTED CIRCUIT BOARD
Venkel Venkel Venkel
2340-6111TN or 2380-6121TN 3M 901-10003 1729018 CR1206-8W-000T CR0603-16W-1002FT CR0603-16W-2551FT MAX6376XR23-T SI5018-BM SI5018-EVB PCB Rev C Amphenol
Phoenix Contact
Venkel Venkel Venkel Maxim Silicon Laboratories Silicon Laboratories
SPARE,0805
Rev. 1.0
5
SI5018-EVB
Figure 3. Si5018 Silkscreen
6
Rev. 1.0
SI5018-EVB
Figure 4. Si5018 Component Side
Rev. 1.0
7
SI5018-EVB
Figure 5. Solder Side
8
Rev. 1.0
SI5018-EVB
Document Change List
Revision 0.41 to Revision 1.0
"Preliminary" language removed.
Evaluation Board Assembly Revision History
Assembly Level A-01 B-01 B-02 PCB A B C Si5018 Device A B B Assembly Notes Assemble per BOM rev A-01. Assemble per BOM rev B-01. Assemble per BOM rev B-02.
Rev. 1.0
9
SI5018-EVB
Contact Information
Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and SiPHY are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
10
Rev. 1.0

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